/*
 * Various feature switches for the 1-lane PCIe controller on Pi 5
 */

/dts-v1/;
/plugin/;

/ {
	compatible = "brcm,bcm2712";

	/* Enable L1 sub-state support */
	fragment@0 {
		target = <&pciex1>;
		__dormant__ {
			brcm,clkreq-mode = "default";
		};
	};

	/* Disable ASPM L0s */
	fragment@1 {
		target = <&pciex1>;
		__dormant__ {
			aspm-no-l0s;
		};
	};

	/* Use RC MSI target instead of MIP MSIx target */
	fragment@2 {
		target = <&pciex1>;
		__dormant__ {
			msi-parent = <&pciex1>;
		};
	};

	/*
	 * Shift the start of the 32bit outbound window to 2GB,
	 * so there are no BARs starting at 0x0. Expand the 64bit
	 * outbound window to use the spare 2GB.
	 */
	fragment@3 {
		target = <&pciex1>;
		__dormant__ {
			#address-cells = <3>;
			#size-cells = <2>;
			ranges = <0x02000000 0x00 0x80000000
				  0x1b 0x80000000
				  0x00 0x7ffffffc>,
				 <0x43000000 0x04 0x00000000
				  0x18 0x00000000
				  0x03 0x80000000>;
		};
	};

	__overrides__ {
		l1ss = <0>, "+0";
		no-l0s = <0>, "+1";
		no-mip = <0>, "+2";
		mmio-hi = <0>, "+3";
	};
};