Index of /buildroot-dl/linux/git/drivers/accel/habanalabs/include/goya/asic_reg/
../
cpu_ca53_cfg_masks.h 29-May-2026 10:53 11K
cpu_ca53_cfg_regs.h 29-May-2026 10:53 2020
cpu_if_regs.h 29-May-2026 10:53 1520
cpu_pll_regs.h 29-May-2026 10:53 3733
dma_ch_0_masks.h 29-May-2026 10:53 19K
dma_ch_0_regs.h 29-May-2026 10:53 7848
dma_ch_1_regs.h 29-May-2026 10:53 7848
dma_ch_2_regs.h 29-May-2026 10:53 7848
dma_ch_3_regs.h 29-May-2026 10:53 7848
dma_ch_4_regs.h 29-May-2026 10:53 7848
dma_macro_masks.h 29-May-2026 10:53 4146
dma_macro_regs.h 29-May-2026 10:53 6749
dma_nrtr_masks.h 29-May-2026 10:53 10K
dma_nrtr_regs.h 29-May-2026 10:53 8560
dma_qm_0_masks.h 29-May-2026 10:53 23K
dma_qm_0_regs.h 29-May-2026 10:53 6661
dma_qm_1_regs.h 29-May-2026 10:53 6661
dma_qm_2_regs.h 29-May-2026 10:53 6661
dma_qm_3_regs.h 29-May-2026 10:53 6661
dma_qm_4_regs.h 29-May-2026 10:53 6661
goya_blocks.h 29-May-2026 10:53 81K
goya_masks.h 29-May-2026 10:53 10K
goya_regs.h 29-May-2026 10:53 3647
ic_pll_regs.h 29-May-2026 10:53 3729
mc_pll_regs.h 29-May-2026 10:53 3729
mme1_rtr_masks.h 29-May-2026 10:53 36K
mme1_rtr_regs.h 29-May-2026 10:53 12K
mme2_rtr_regs.h 29-May-2026 10:53 12K
mme3_rtr_regs.h 29-May-2026 10:53 12K
mme4_rtr_regs.h 29-May-2026 10:53 12K
mme5_rtr_regs.h 29-May-2026 10:53 12K
mme6_rtr_regs.h 29-May-2026 10:53 12K
mme_cmdq_masks.h 29-May-2026 10:53 19K
mme_cmdq_regs.h 29-May-2026 10:53 5023
mme_masks.h 29-May-2026 10:53 83K
mme_qm_masks.h 29-May-2026 10:53 23K
mme_qm_regs.h 29-May-2026 10:53 6575
mme_regs.h 29-May-2026 10:53 44K
mmu_masks.h 29-May-2026 10:53 7476
mmu_regs.h 29-May-2026 10:53 1663
pci_nrtr_masks.h 29-May-2026 10:53 10K
pci_nrtr_regs.h 29-May-2026 10:53 8254
pcie_aux_regs.h 29-May-2026 10:53 9193
pcie_wrap_regs.h 29-May-2026 10:53 11K
psoc_emmc_pll_regs.h 29-May-2026 10:53 3757
psoc_etr_regs.h 29-May-2026 10:53 4178
psoc_global_conf_masks.h 29-May-2026 10:53 25K
psoc_global_conf_regs.h 29-May-2026 10:53 28K
psoc_mme_pll_regs.h 29-May-2026 10:53 3753
psoc_pci_pll_regs.h 29-May-2026 10:53 3753
psoc_spi_regs.h 29-May-2026 10:53 5238
psoc_timestamp_regs.h 29-May-2026 10:53 1871
sram_y0_x0_rtr_regs.h 29-May-2026 10:53 2895
sram_y0_x1_rtr_regs.h 29-May-2026 10:53 2895
sram_y0_x2_rtr_regs.h 29-May-2026 10:53 2895
sram_y0_x3_rtr_regs.h 29-May-2026 10:53 2895
sram_y0_x4_rtr_regs.h 29-May-2026 10:53 2895
stlb_masks.h 29-May-2026 10:53 5432
stlb_regs.h 29-May-2026 10:53 1747
tpc0_cfg_masks.h 29-May-2026 10:53 79K
tpc0_cfg_regs.h 29-May-2026 10:53 34K
tpc0_cmdq_masks.h 29-May-2026 10:53 19K
tpc0_cmdq_regs.h 29-May-2026 10:53 5085
tpc0_eml_cfg_masks.h 29-May-2026 10:53 18K
tpc0_eml_cfg_regs.h 29-May-2026 10:53 12K
tpc0_nrtr_masks.h 29-May-2026 10:53 10K
tpc0_nrtr_regs.h 29-May-2026 10:53 8564
tpc0_qm_masks.h 29-May-2026 10:53 23K
tpc0_qm_regs.h 29-May-2026 10:53 6657
tpc1_cfg_regs.h 29-May-2026 10:53 34K
tpc1_cmdq_regs.h 29-May-2026 10:53 5085
tpc1_qm_regs.h 29-May-2026 10:53 6657
tpc1_rtr_regs.h 29-May-2026 10:53 12K
tpc2_cfg_regs.h 29-May-2026 10:53 34K
tpc2_cmdq_regs.h 29-May-2026 10:53 5085
tpc2_qm_regs.h 29-May-2026 10:53 6657
tpc2_rtr_regs.h 29-May-2026 10:53 12K
tpc3_cfg_regs.h 29-May-2026 10:53 34K
tpc3_cmdq_regs.h 29-May-2026 10:53 5085
tpc3_qm_regs.h 29-May-2026 10:53 6657
tpc3_rtr_regs.h 29-May-2026 10:53 12K
tpc4_cfg_regs.h 29-May-2026 10:53 34K
tpc4_cmdq_regs.h 29-May-2026 10:53 5085
tpc4_qm_regs.h 29-May-2026 10:53 6657
tpc4_rtr_regs.h 29-May-2026 10:53 12K
tpc5_cfg_regs.h 29-May-2026 10:53 34K
tpc5_cmdq_regs.h 29-May-2026 10:53 5085
tpc5_qm_regs.h 29-May-2026 10:53 6657
tpc5_rtr_regs.h 29-May-2026 10:53 12K
tpc6_cfg_regs.h 29-May-2026 10:53 34K
tpc6_cmdq_regs.h 29-May-2026 10:53 5085
tpc6_qm_regs.h 29-May-2026 10:53 6657
tpc6_rtr_regs.h 29-May-2026 10:53 12K
tpc7_cfg_regs.h 29-May-2026 10:53 34K
tpc7_cmdq_regs.h 29-May-2026 10:53 5085
tpc7_nrtr_regs.h 29-May-2026 10:53 8564
tpc7_qm_regs.h 29-May-2026 10:53 6657
tpc_pll_regs.h 29-May-2026 10:53 3733