# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3128-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip RK3126/RK3128 Clock and Reset Unit (CRU)

maintainers:
  - Elaine Zhang <zhangqing@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |
  The RK3126/RK3128 clock controller generates and supplies clock to various
  controllers within the SoC and also implements a reset controller for SoC
  peripherals.
  Each clock is assigned an identifier and client nodes can use this identifier
  to specify the clock which they consume. All available clocks are defined as
  preprocessor macros in the dt-bindings/clock/rk3128-cru.h headers and can be
  used in device tree sources. Similar macros exist for the reset sources in
  these files.

properties:
  compatible:
    enum:
      - rockchip,rk3126-cru
      - rockchip,rk3128-cru

  reg:
    maxItems: 1

  "#clock-cells":
    const: 1

  "#reset-cells":
    const: 1

  clocks:
    minItems: 1
    maxItems: 3

  clock-names:
    minItems: 1
    items:
      - const: xin24m
      - enum:
          - ext_i2s
          - gmac_clkin
      - enum:
          - ext_i2s
          - gmac_clkin

  rockchip,grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to the syscon managing the "general register files" (GRF),
      if missing pll rates are not changeable, due to the missing pll
      lock status.

required:
  - compatible
  - reg
  - "#clock-cells"
  - "#reset-cells"

additionalProperties: false

examples:
  - |
    cru: clock-controller@20000000 {
      compatible = "rockchip,rk3128-cru";
      reg = <0x20000000 0x1000>;
      rockchip,grf = <&grf>;
      #clock-cells = <1>;
      #reset-cells = <1>;
    };
