# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm4450-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display Clock & Reset Controller on SM4450

maintainers:
  - Ajit Pandey <quic_ajipan@quicinc.com>
  - Taniya Das <quic_tdas@quicinc.com>

description: |
  Qualcomm display clock control module provides the clocks, resets and power
  domains on SM4450

  See also:: include/dt-bindings/clock/qcom,sm4450-dispcc.h

properties:
  compatible:
    const: qcom,sm4450-dispcc

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Board XO source
      - description: Board active XO source
      - description: Display AHB clock source from GCC
      - description: sleep clock source
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

  '#power-domain-cells':
    const: 1

required:
  - compatible
  - reg
  - clocks
  - '#clock-cells'
  - '#reset-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/clock/qcom,sm4450-gcc.h>
    clock-controller@af00000 {
      compatible = "qcom,sm4450-dispcc";
      reg = <0x0af00000 0x20000>;
      clocks = <&rpmhcc RPMH_CXO_CLK>,
               <&rpmhcc RPMH_CXO_CLK_A>,
               <&gcc GCC_DISP_AHB_CLK>,
               <&sleep_clk>,
               <&dsi0_phy_pll_out_byteclk>,
               <&dsi0_phy_pll_out_dsiclk>;
      #clock-cells = <1>;
      #reset-cells = <1>;
      #power-domain-cells = <1>;
    };
...
